Digital Electronics - Logic Gates - Discussion

2. 

The gates in this figure are implemented using TTL logic. If the output of the inverter is open, and you apply logic pulses to point B, the output of the AND gate will be ________.

[A]. a steady LOW
[B]. a steady HIGH
[C]. an undefined level
[D]. pulses

Answer: Option D

Explanation:

No answer description available for this question.

Shobha Pathare said: (Jan 9, 2014)  
If the o/p of inverter is open that means 0 and for B I/p is pulse means 1 so the o/p become 0.

Shan said: (Nov 7, 2014)  
How to get pulses because one of the input is open it means "0" so output should be 0?

Anand said: (Nov 29, 2015)  
Doesn't 'open' mean no current in that wire i.e. HighZ, makes first input undriven.

Answer should be "an Undefined level".

Anuj said: (Nov 28, 2019)  
In TTL an open terminal is always "high" 1. So B will be at the output. B= pulses.

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