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Digital Electronics - Flip-Flops - Discussion

Discussion Forum : Flip-Flops - General Questions (Q.No. 59)
Flip-Flops
59.
A positive edge-triggered J-K flip-flop is used to produce a two-phase clock. However, when the circuit is operated it produces erratic results. Close examination with a scope reveals the presence of glitches. What causes the glitches, and how might the problem be corrected?
The PRESET and CLEAR terminals may have been left floating; they should be properly terminated if not being used.
The problem is caused by a race condition between the J and K inputs; an inverter should be inserted in one of the terminals to correct the problem.
A race condition exists between the Q and Q outputs to the AND gate; the AND gate should be replaced with a NAND gate.
A race condition exists between the clock and the outputs of the flip-flop feeding the AND gate; replace the flip-flop with a negative edge-triggered J-K Flip-Flop.
Answer: Option
Explanation:
No answer description is available. Let's discuss.
Discussion:
6 comments Page 1 of 1.
Hemu said:   1 decade ago
Please explain this.
Meesha said:   1 decade ago
Please explain.
Prem kumar said:   1 decade ago
Please explain how NOT gates acts as invertor ?
Akshit Jain said:   1 decade ago
@Prem Kumar.

Invertor logic is : f = not(A).

So NOT gate Acts as an Invertor.
Radhika said:   1 decade ago
Answer should be A according to me because preset and clear terminals are the reason of asynchronization and hence they produces glitches if they are not being used then they must be terminated.
Raviraj said:   10 years ago
Answer should be A because race around condition in J K f/f occurs only in level triggering.
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