Digital Electronics - Flip-Flops - Discussion
Discussion Forum : Flip-Flops - General Questions (Q.No. 71)
71.
The circuit given below fails to function; the inputs are checked with a logic probe and the following indications are obtained: CLK, J1, J2, J3, K1, K2, and K3 are pulsing. Q and 
are HIGH. 
and PRE are LOW. What could be causing the problem?
Discussion:
6 comments Page 1 of 1.
Sandhya said:
1 decade ago
Someone please explain it.
Sona said:
1 decade ago
What is PRE input for?
Sahana said:
1 decade ago
If the preset kept low the output(Q) will always be 1. So it is causing problem.
Sanchita said:
1 decade ago
What is preset?
Rushit said:
1 decade ago
If preset pin pin is low or high according to the logic used (here it is negative logic so low) then it sets the output (i.e. Q=1) in advance whether the clock is applied or not.
Yaswant said:
8 years ago
Preset and clear are asynchronous inputs to a flip-flop.
If the preset and clear are low it gives race around condition so, preset and clear should never below.
Preset is used to set the flip-flop to previous state ie,1.
If the preset and clear are low it gives race around condition so, preset and clear should never below.
Preset is used to set the flip-flop to previous state ie,1.
(1)
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