Digital Electronics - Counters

Exercise :: Counters - General Questions

37. 

A 4-bit up/down binary counter is in the DOWN mode and in the 1100 state. To what state does the counter go on the next clock pulse?

A. 1101
B. 1011
C. 1111
D. 0000

Answer: Option B

Explanation:

No answer description available for this question. Let us discuss.

38. 

A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ________.

A. 15 ns
B. 30 ns
C. 45 ns
D. 60 ns

Answer: Option D

Explanation:

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39. 

The terminal count of a 3-bit binary counter in the DOWN mode is ________.

A. 000
B. 111
C. 101
D. 010

Answer: Option A

Explanation:

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40. 

The hexadecimal equivalent of 15,536 is ________.

A. 3CB0
B. 3C66
C. 63C0
D. 6300

Answer: Option A

Explanation:

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41. 

In an HDL ring counter, many invalid states are included in the programming by:

A. using a case statement.
B. using an elsif statement.
C. including them under others.
D. the ser_in line.

Answer: Option C

Explanation:

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42. 

In a VHDL retriggerable edge-triggered one-shot, which condition will not exist when a clock edge occurs?

A. A trigger edge has occurred and we must load the counter.
B. The counter is zero and we need to keep it at zero.
C. The shift register is reset.
D. The counter is not zero and we need to count down by one.

Answer: Option C

Explanation:

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