IndiaBIX

Digital Electronics - Counters

Exercise : Counters - General Questions
26.
For a multistage counter to be truly synchronous, the ________ of each stage must be connected to ________.
Cp, the same clock input line
CE, the same clock input line
, the terminal count output
, both clock input lines
Answer: Option
Explanation:
No answer description is available. Let's discuss.
27.
Which of the following is an invalid output state for an 8421 BCD counter?
1110
0000
0010
0001
Answer: Option
Explanation:
No answer description is available. Let's discuss.
28.
How many different states does a 3-bit asynchronous counter have?
2
4
8
16
Answer: Option
Explanation:
No answer description is available. Let's discuss.
29.
A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (tp(tot)) is ________.
12 ms
24 ns
48 ns
60 ns
Answer: Option
Explanation:
No answer description is available. Let's discuss.
30.

A four-channel scope is used to check the counter in the figure given below. Are the displayed waveforms correct?

Yes
No
Answer: Option
Explanation:
No answer description is available. Let's discuss.
Quick links
Quantitative Aptitude
Verbal (English)
Reasoning
Programming
Interview
Placement Papers