# Electronics - Sequential Logic Circuits

### Exercise :: Sequential Logic Circuits - Filling the Blanks

1.

Synchronous construction reduces the delay time of a counter to the delay of __________.

 A. all flip-flops and gates B. a single flip-flop and a gate C. all flip-flops and gates after a 3 count D. a single gate

Explanation:

No answer description available for this question. Let us discuss.

2.

A 4-bit PISO shift register that receives 4 bits of parallel data will shift to the ________ by ________ position(s) for each clock pulse.

 A. right, one B. right, two C. left, one D. left, three

Explanation:

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3.

To operate correctly, starting a ring counter requires __________.

 A. clearing one flip-flop and presetting all the others B. clearing all the flip-flops C. presetting one flip-flop and clearing all the others D. presetting all the flip-flops

Explanation:

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4.

In order to use a shift register as a counter, ________.

 A. the register's serial input is the counter input and the serial output is the counter output B. the parallel inputs provide the input signal and the output signal is taken from the serial data output C. a serial-in, serial-out register must be used D. the serial output of the register is connected back to the serial input of the register

Explanation:

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5.

A sequence of equally spaced timing pulses may be easily generated by a(n) __________.

 A. ring counter B. johnson counter C. binary up counter D. ripple counter