Electronics - Flip-Flops and Timers - Discussion
Discussion Forum : Flip-Flops and Timers - General Questions (Q.No. 14)
14.
What is one disadvantage of an S-R flip-flop?
Discussion:
10 comments Page 1 of 1.
Karuppasamy k.p.k said:
1 decade ago
plz... Explain "Race" condition.
Priya said:
1 decade ago
Could you explain the race condition ?
Sobersh said:
1 decade ago
What is race condition ?
Sreevishakh said:
1 decade ago
I think they are telling about "race around condition". It means condition when the two inputs race themselves for influencing the o/p for further search wiki.
Shweta said:
1 decade ago
Race around condition is the drawback of j-k flip flop not of s-r flip flop. The main drawback of s-r flip flop is invalid output when both the inputs are high. In j k flip flop, race around condition is explained as," when duration of input change is less than that of clock pulse, then we cannot get the proper output, as output feeds back to input in j k flip flop. to avoid this problem, master slave flip flop is invented."
Swapnil rai said:
1 decade ago
Race around problem is only created in J-K flip flop where the value of J=1 and K=1, it become toggle then race condition is not a part of S-R flip flop.
Sandeep said:
10 years ago
Race condition means in SR flip flop we will get same value for both Q and ~Q.
That is why we call it as race condition.
That is why we call it as race condition.
Dharani said:
8 years ago
Race condition means the o/p will change like toggle condition in an uncontrolled manner (rapid change) that's why race must be avoided.
BALAJI said:
6 years ago
Race condition means when both the input of SR flip flop is logic 1 then output Qn and Qn+1 is unpredictable.
This overcomes in JK flip flop when both the input of SR flip flop is logic 1 then output Qn and Qn+1 is toggle.
This overcomes in JK flip flop when both the input of SR flip flop is logic 1 then output Qn and Qn+1 is toggle.
Chaithaya said:
5 years ago
The one major disadvantage of the s-r flip flop is that in the condition when the clock is triggered the inputs become high which is an undesirable condition because it causes invalid input, the condition in which you can't predict the output.
Post your comments here:
Quick links
Quantitative Aptitude
Verbal (English)
Reasoning
Programming
Interview
Placement Papers