Electronics - Flip-Flops and Timers - Discussion
Discussion Forum : Flip-Flops and Timers - General Questions (Q.No. 7)
7.
If both inputs of an S-R NAND latch are LOW, what will happen to the output?
Discussion:
8 comments Page 1 of 1.
Kalyan said:
1 decade ago
When both inputs of an SR nand latch are low, the outputs both are high because the output of a nand gate is high if any input is zero.
So, this answer is not there.
So, this answer is not there.
Triparna said:
1 decade ago
I didn't understand this. Can anyone please explain this ?
Shubha said:
1 decade ago
When both i/ps of SR NAND latch is low then no change will occur in the o/p.
Kaushal said:
1 decade ago
When any i/p of SR NAND is low then o/p goes high, so when one i/p of both NAND gates is low then the o/p of both gates is high,that is not acceptable. so Ans. is [A].
Anshi said:
1 decade ago
Truth table of sr flip flop:
s r Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 unpredictable
Truth table of NAND
A B o/p
0 0 1
0 1 1
1 0 1
1 1 0
It is clear from truth table of NAND gate when any one i/p is 0 or low than o/p is 1 so in our case o/p=1.
So both the i/p of SR FF are 1 so 'unpredictable' .
s r Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 unpredictable
Truth table of NAND
A B o/p
0 0 1
0 1 1
1 0 1
1 1 0
It is clear from truth table of NAND gate when any one i/p is 0 or low than o/p is 1 so in our case o/p=1.
So both the i/p of SR FF are 1 so 'unpredictable' .
(1)
Prashant Goad said:
1 decade ago
NAND Gate is active low.
Its provide the output excitedly reverse of NOR gate.
In NOR Gate when i/p is 00 output is No CHANGE but i/p is 11 its unpredictable, so it reverse in NAND Gate.
Its provide the output excitedly reverse of NOR gate.
In NOR Gate when i/p is 00 output is No CHANGE but i/p is 11 its unpredictable, so it reverse in NAND Gate.
Zil-e-Huma said:
10 years ago
When both inputs of an SR latch are low then output remains as it is i.e. doesn't change. It gives unpredictable output when both inputs are high.
So the answer is wrong.
So the answer is wrong.
Ankit said:
9 years ago
When S and R are both are low output will obviously the same as previous.
Low input to NAND gives high output that is S = 0 and R = 0 will give high output. There is no change in NAND S-R latch.
Low input to NAND gives high output that is S = 0 and R = 0 will give high output. There is no change in NAND S-R latch.
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