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Electronics and Communication Engineering - Electronic Devices and Circuits

Exercise : Electronic Devices and Circuits - Section 6
21.

Assertion (A): Master slave JK flip flop is commonly used in high speed synchronous circuitry

Reason (R): Master slave JK flip flop uses two JK flip flops in cascade.

Both A and R are correct and R is correct explanation of A
Both A and R are correct but R is not correct explanation of A
A is true, R is false
A is false, R is true
Answer: Option
Explanation:

R-S, J-K flip-flop is not used very commonly.

22.
Inputs A and B of the given figure are applied to a NAND gate. The output is LOW
from 0 to 6
from 0 to 2
from 0 to 1 and 2 to 3
from 1 to 2 and 3 to 4
Answer: Option
Explanation:

NAND gate gives Low output if all inputs are High. For other combinations of inputs, output is High.

23.
ECL is a saturating logic.
True
False
Answer: Option
Explanation:

It is a non-saturating logic. Hence highest speed of operation.

24.
For the NMOS gate in the given figure, F =
ABCDE
(AB + C) (D + E)
A(B + C) + DE
A + B C + DE
Answer: Option
Explanation:

B + C are in parallel and A is in series with this parallel combination, Similarly D + E are in series. Then D, E are in parallel with A, B and C Y = A(B + C) + DE .

25.
The resolution of 4 bit counting ADC is 0.5 volt, for an Analog input of 6.6 volts. The digital output of ADC will be
1011
1101
1100
1110
Answer: Option
Explanation:

Digital output of ADC resolution = .

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