Electronics and Communication Engineering - Digital Electronics - Discussion
Discussion Forum : Digital Electronics - Section 8 (Q.No. 41)
41.
In a 4 bit counter the output of 3 JK FFs from MSB downward are connected to the NAND gate whose O/P is connected to CLR
Discussion:
2 comments Page 1 of 1.
Alpesh said:
8 years ago
Please explain this.
(1)
Christian ramas said:
6 years ago
MOD 15 because it resets at 1110 if starts at MSB.
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