Electronics and Communication Engineering - Digital Electronics - Discussion

30. 

The open collector gates in the given figure are tied together. The output Y =

[A]. A + B + C + D
[B]. A + B + C + D
[C]. (A + B) (C + D)
[D]. AB + CD

Answer: Option A

Explanation:

No answer description available for this question.

Diwakar said: (Jun 10, 2014)  
Open collector TTL provides wired AND logic at output not OR.

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