Electronics and Communication Engineering - Digital Electronics - Discussion

5. 

In a D latch

[A]. data bit D is fed to S input and D to R input
[B]. data bit D is fed to R input and D to S input
[C]. data bit D is fed to both R and S inputs
[D]. data bit D is not fed to any input

Answer: Option A

Explanation:


Suki said: (Dec 7, 2016)  
As per my knowledge, the Question is incomplete because latch can be designed by using NAND and NOR gates. In SR latch S&R position depends on NAND & NOR gates.

Hari said: (Aug 4, 2018)  
R is the first input and S is the second input.

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