Digital Electronics - Shift Registers - Discussion
Discussion Forum : Shift Registers - Filling the Blanks (Q.No. 5)
5.
An 8-bit serial in/parallel out shift register is clocked at 4 MHz and is used to delay a serial digital signal by 1.25 
s. The output that has the proper delay is ________.
s. The output that has the proper delay is ________.Discussion:
2 comments Page 1 of 1.
Khitab said:
1 decade ago
Can anyone explain this?
KIRAN V said:
5 years ago
Given: f = 4 MHz; t = 1.25 μs; n =?
f = n/t.
4 MHz = n / 1.25 μs,
n = 5 --> QE.
f = n/t.
4 MHz = n / 1.25 μs,
n = 5 --> QE.
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