Digital Electronics - Shift Registers

Exercise :: Shift Registers - Filling the Blanks

1. 

Assume a LOW logic level is placed on the SHIFT/LOAD input of a 74195 shift register. The output will change ________.

A. immediately
B. if the CLOCK is also LOW
C. on the next clock leading edge
D. depending on the J and K inputs

Answer: Option C

Explanation:

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2. 

A type of shift register in which the Q or Q output of one stage is not connected to the input of the next stage is ________.

A. parallel in/serial out
B. serial in/parallel out
C. serial in/serial out
D. parallel in/parallel out

Answer: Option D

Explanation:

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3. 

A Johnson counter, constructed with N flip-flops, has how many unique states?

A. N
B. 2N
C. 2N
D. N2

Answer: Option B

Explanation:

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4. 

A type of shift register that requires access to the Q outputs of all stages is ________.

A. parallel in/serial out
B. serial in/parallel out
C. serial in/serial out
D. a bidirectional shift register

Answer: Option B

Explanation:

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5. 

An 8-bit serial in/parallel out shift register is clocked at 4 MHz and is used to delay a serial digital signal by 1.25 s. The output that has the proper delay is ________.

A. QE
B. QF
C. QG
D. QH

Answer: Option A

Explanation:

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