Digital Electronics - Flip-Flops - Discussion
Discussion Forum : Flip-Flops - General Questions (Q.No. 48)
48.
What is one disadvantage of an S-R flip-flop?
Discussion:
5 comments Page 1 of 1.
Pranav said:
9 years ago
When we give inputs to SR flip-flop, the outputs we get should be a compliment. That's is Q and Q' When S and R are high (S=R= 1),
The o/p is Q=0 and Q'=0. That's why it's called invalid state.
The o/p is Q=0 and Q'=0. That's why it's called invalid state.
Shiv said:
1 decade ago
When both inputs of SR flip flops are high i.e. S = 1 and R = 1, the state in which FF goes is called as an invalid state.
Madasusatya said:
1 decade ago
What does invalid state means ?
Krishna said:
1 decade ago
What is mean by invalid state. ?
Venkat said:
1 decade ago
What is mean invalid state?
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