Digital Electronics - Flip-Flops - Discussion
Discussion Forum : Flip-Flops - General Questions (Q.No. 10)
10.
The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ________.
Discussion:
5 comments Page 1 of 1.
Mounika said:
5 years ago
By using parity check also we can interpret the unwanted signal right, then Why only ones catching? Please explain in detail.
CHAITHRA said:
7 years ago
I didn't understand. Can anyone explain in a simple way?
Sai said:
1 decade ago
Is that means all sr flip flops comes under this section?
Muskaan said:
1 decade ago
The "catching" issue has to do with short-term glitches, not with the well-known indeterminate states of SR or JK flip-flops. Even a master-slave JK flip-flop, under the right conditions, will set or clear if an input is glitched. Ones-catching means that the input transitioned to a 1 and back very briefly (unintentionally due to a glitch), but the flip-flop responded and latched it in anyway, i.e., it caught the 1. Similarly for 0's catching.
The interior of the JK flip flop still has asynchronous bi-stables made from either NANDs or NORs. The NAND will catch ones, the NOR will catch zeroes.
The interior of the JK flip flop still has asynchronous bi-stables made from either NANDs or NORs. The NAND will catch ones, the NOR will catch zeroes.
(1)
Darnasinarendra said:
1 decade ago
I couldn't understand the meaning of the question. Can anyone tell the meaning?
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