Digital Electronics - Flip-Flops - Discussion

Discussion Forum : Flip-Flops - General Questions (Q.No. 50)
50.
What is one disadvantage of an S-R flip-flop?
It has no enable input.
It has an invalid state.
It has no clock input.
It has only a single output.
Answer: Option
Explanation:
No answer description is available. Let's discuss.
Discussion:
2 comments Page 1 of 1.

Attahir S Abba said:   1 decade ago
This is referred to as critical race. That is a change in two input variables that results in an unpredictable output value for a bis-table device like this SR flip flop.

Anup Kumar said:   1 decade ago
When both S=1 and R=1 the occurrence of a clock pulse causes both outputs to go to 0 (zero) and when the pulse is removed the state of the flip-flop is indeterminate or invalid as shown in answer B.

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