IndiaBIX

Digital Electronics - Digital Arithmetic Operations and Circuits - Discussion

Discussion Forum : Digital Arithmetic Operations and Circuits - General Questions (Q.No. 57)
Digital Arithmetic Operations and Circuits
57.
In VHDL, what is a GENERATE statement?
The start statement of a program
Not used in VHDL or ADHL
A way to get the computer to generate a program from a circuit diagram
A way to tell the compiler to replicate several components
Answer: Option
Explanation:
No answer description is available. Let's discuss.
Discussion:
2 comments Page 1 of 1.
Megha said:   1 decade ago
Which are other statements?
Pvkrishna said:   8 years ago
Generate statement is usually used to instantiate "arrays" of components. The generated parameter may be used to index array-type signals associated with component ports. Generate statement is particularly powerful when used with integer generics.
Post your comments here:

Your comments will be displayed after verification.

Quick links
Quantitative Aptitude
Verbal (English)
Reasoning
Programming
Interview
Placement Papers