Digital Electronics - Counters - Discussion

Discussion Forum : Counters - General Questions (Q.No. 17)
17.

What decimal value is required to produce an output at "X" ?

1
1 or 4
2
5
Answer: Option
Explanation:
No answer description is available. Let's discuss.
Discussion:
13 comments Page 1 of 2.

Ponni said:   1 decade ago
Output of q2=1, q1=0 & q0=1, then in binary 101 represents 5in decimal value.

Swar said:   1 decade ago
j=k=high,so output is toggle.Toggle means complement of previous output.
suppose previous output zero ,the output of q2=1,q1=0&q=1. The output of X=5.
Otherwise=>010=>2

MOHIT PRAKASH MISHRA said:   1 decade ago
The given counter arrangement is asynchronous counter and this is jk flip flop which in toggle condition sn the output of Q2 is 1 and Q0. Is 1 and Q1 toggle when clk pulse is high so it's o/p is 0 so answer is 101=5.
(2)

Satyendra singh said:   1 decade ago
For AND gate if all input is high '1' then o/p is high.
Otherwise low '0';

For o/p '1' means(here x o/p).
All i/p must be '1';

Also in this ckt mention that.
Here,
For Q0 = 1.
Q1 = 0(bcg ~Q=1).

Q2 = 1 then.
o/p is 'high' or 'X'.

Siva chithra said:   1 decade ago
Please give me the correct explanation sir.

Kavi said:   1 decade ago
I couldn't understand can anyone explain clearly?

Vinay said:   1 decade ago
I want to get a right answer please explain anyone.

Nitin said:   10 years ago
Please explain anyone?

Madhuri said:   9 years ago
JK flip-flop operation.

Here, notice that both the inputs i.e., J and K are tied together and given. Therefore the only possible input conditions for JK flipflop are (j=0& k=0) or (j =1 and k=1).

Now we are in J=1, K=1 condition, which means the present output Q should be the toggled version of previous state output.

The previous state output will obviously be for j= 0 and k=0 input condition. The output, in this case, will be 0 only (retains the previous state for j=0 and k=0 condition) - check truth table for jk flip flop.

This is how the first flip flop's output becomes 1 (toggle of previous state output 5, 0).

Now consider second flip-flop, the same condition repeats but the output is taken from Qbar pin of the flipflop. Therefore second flipflop's output is 0.

The third one follows similar explanation as given for first flip-flop. Output turns out to be 1 again.
(1)

HARINI said:   8 years ago
The given ckt is 3-bit ripple counter.

This counter o/p takes from Q0, Q1 & Q2.
it counts from 000 to 111 all these 3 o/p Q0, Q1^ & Q2 are giving to AND gate it produces X o/p.
For AND gate if all input is high '1' then o/p is high Otherwise low '0';
For o/p X '1' means(here x is AND o/p).
for this ckt

Q0 Q1^ Q2
1 0 1
only at this state all i/p of AND connected to ligic1.
so X is high only at this state.
its decimal value is 5.
Answer is 5.

All i/p must be '1'.


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