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Digital Electronics - Counters

Exercise : Counters - General Questions
46.

Referring to the given figure, what causes the Control FF to reset after D7?

Once the data cycle is initiated by the Start bit, the one-shot produces an output pulse equal to the duration of the eight data bits. Once the eight data bits have been transferred to the data input register, the falling edge of the one-shot pulse resets the Control FF to start the sequence all over again.
After counting the eight data bits, the divide-by-8 counter produces an output on its active-LOW CLR line to reset the Control FF.
After counting eight clock pulses equivalent to eight data periods, the terminal count of the divide-by-8 counter and the clock trigger the one-shot, which in turn resets the Control FF and divide-by-8 circuits to begin the sequence all over again. Simultaneously the data is transferred through the output register.
When the data output register is full, it produces an output on its C terminal that triggers the one-shot, which in turn resets the Control FF.
Answer: Option
Explanation:
No answer description is available. Let's discuss.
47.

What function will the counter shown below be performing during period "B" on the timing diagram?

Counting up
Counting down
Inhibited
Loading
Answer: Option
Explanation:
No answer description is available. Let's discuss.
48.
Three cascaded decade counters will divide the input frequency by ________.
10
20
100
1,000
Answer: Option
Explanation:
No answer description is available. Let's discuss.
49.
A counter with a modulus of 16 acts as a ________.
divide-by-8 counter
divide-by-16 counter
divide-by-32 counter
divide-by-64 counter
Answer: Option
Explanation:
No answer description is available. Let's discuss.
50.

How many data bits can be stored in the register shown below?

5
32
31
4
Answer: Option
Explanation:
No answer description is available. Let's discuss.
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