Digital Electronics - Combinational Logic Circuits - Discussion

36. 

In VHDL, data can be each of the following types except ________.

[A]. BIT
[B]. BIT_VECTOR
[C]. STD_LOGIC
[D]. STD_VECTOR

Answer: Option D

Explanation:

No answer description available for this question.

Post your comments here:

Name *:

Email   : (optional)

» Your comments will be displayed only after manual approval.