IndiaBIX

Electronics - Standard Logic Devices (SLD)

Exercise : Standard Logic Devices (SLD) - Filling the Blanks
1.
PMOS and NMOS ____________________________.
represent MOSFET devices utilizing either P-channel or N-channel devices exclusively within a given gate
are enhancement type CMOS devices used to produce a series of high-speed logic known as 74HC
represent positive and negative MOS type devices that can be operated from differential power supplies and are compatible with operational amplifiers
none of the above
Answer: Option
Explanation:
No answer description is available. Let's discuss.
2.
The number of inputs that a gate output can drive without possible logic errors is the _______.
propagation delay
noise margin
speed-power product
fanout
Answer: Option
Explanation:
No answer description is available. Let's discuss.
3.
In order to get a HIGH or a LOW output from an open-collector gate, an external _________ must be connected between +VCC and the collector.
pull-down resistor
pull-up resistor
diode
buffer
Answer: Option
Explanation:
No answer description is available. Let's discuss.
4.
An undefined state, neither high nor low, is called _________.
don't care
floating
minimum state
noise
Answer: Option
Explanation:
No answer description is available. Let's discuss.
5.
When the output of a standard TTL gate is HIGH, it can ___________________.
sink 16 mA of current from the attached input gates
source 400 mu.gifA of current to no more than 10 attached gates
source 16 mA of current to no more than 10 attached gates
sink a maximum of 400 mu.gifA from no more than 10 load gates
Answer: Option
Explanation:
No answer description is available. Let's discuss.
Quick links
Quantitative Aptitude
Verbal (English)
Reasoning
Programming
Interview
Placement Papers