Electronics - Standard Logic Devices (SLD)

Exercise :: Standard Logic Devices (SLD) - Filling the Blanks

1. 

PMOS and NMOS ____________________________.

A. represent MOSFET devices utilizing either P-channel or N-channel devices exclusively within a given gate
B. are enhancement type CMOS devices used to produce a series of high-speed logic known as 74HC
C. represent positive and negative MOS type devices that can be operated from differential power supplies and are compatible with operational amplifiers
D. none of the above

Answer: Option A

Explanation:

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2. 

The number of inputs that a gate output can drive without possible logic errors is the _______.

A. propagation delay
B. noise margin
C. speed-power product
D. fanout

Answer: Option D

Explanation:

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3. 

In order to get a HIGH or a LOW output from an open-collector gate, an external _________ must be connected between +VCC and the collector.

A. pull-down resistor
B. pull-up resistor
C. diode
D. buffer

Answer: Option B

Explanation:

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4. 

An undefined state, neither high nor low, is called _________.

A. don't care
B. floating
C. minimum state
D. noise

Answer: Option B

Explanation:

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5. 

When the output of a standard TTL gate is HIGH, it can ___________________.

A. sink 16 mA of current from the attached input gates
B. source 400 mu.gifA of current to no more than 10 attached gates
C. source 16 mA of current to no more than 10 attached gates
D. sink a maximum of 400 mu.gifA from no more than 10 load gates

Answer: Option B

Explanation:

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