Electronics - Flip-Flops and Timers

Exercise : Flip-Flops and Timers - Filling the Blanks
6.
Pulse-triggered flip-flops are also called _________ flip-flops.
master-slave
postponed
level
edge
Answer: Option
Explanation:
No answer description is available. Let's discuss.

7.
For an S-R flip-flop to be SET or RESET, the respective input must be __________.
LOW
HIGH
installed with steering diodes
in parallel with a limiting resistor
Answer: Option
Explanation:
No answer description is available. Let's discuss.

8.
One example of the use of an S-R flip-flop is as a(n) _________.
racer
binary storage register
astable oscillator
transition pulse generator
Answer: Option
Explanation:
No answer description is available. Let's discuss.

9.
The toggle condition in a master-slave J-K flip-flop means that Q and q.gif will switch to their ________ state(s) at the _____________________.
inverted, positive clock edge
quiescent, negative clock edge
opposite, active clock edge
reset, synchronous clock edge
Answer: Option
Explanation:
No answer description is available. Let's discuss.

10.
If an input is activated by a signal transition, it is _____________.
edge-triggered
toggle-triggered
clock-triggered
noise-triggered
Answer: Option
Explanation:
No answer description is available. Let's discuss.