Electronics and Communication Engineering - Networks Analysis and Synthesis - Discussion

Discussion Forum : Networks Analysis and Synthesis - Section 3 (Q.No. 12)
12.
In a series RLC circuit excited by e = Em sin ωt is seen that LC < 1/ω2. Then
I lags E
I leads E
I leads E are in phase
voltage across L and C are equal
Answer: Option
Explanation:

At frequencies less than resonant frequency current leads voltage.

Discussion:
1 comments Page 1 of 1.

Nishant said:   7 years ago
LC<1/w2.
XL<XC.
The Circuit is capacitive, so I leads E.

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