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Electronics and Communication Engineering - Exam Questions Papers - Discussion

Discussion Forum : Exam Questions Papers - Exam Paper 13 (Q.No. 4)
Exam Questions Papers
4.
For the circuit shown in the figure, D has a transition from 0 to 1 after CLK changes from 1 to 0. Assume gate delays to be negligible

Which of the following statements is true?
Q goes to 1 to the CLK transition and stays at 1
Q goes to 0 at the CLK transition and stays at 10
Q goes to 1 at the CLK transition and goes to 0 when D goes to 1
Q goes to 0 at the CLK transition and goes to 1 when D goes to 1
Answer: Option
Explanation:
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