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Electronics and Communication Engineering - Networks Analysis and Synthesis - Discussion

Discussion Forum : Networks Analysis and Synthesis - Section 8 (Q.No. 21)
Networks Analysis and Synthesis
21.
In the circuit of figure is
I1 will always lag I3
I2 may be in phase or lag I3
I3 will always lag I2
I2 and I3 will be in phase
Answer: Option
Explanation:

I3 is inductive current and must lag I2 which is capacitive current.

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