Electronics and Communication Engineering - Electronic Devices and Circuits
Exercise : Electronic Devices and Circuits - Section 8
- Electronic Devices and Circuits - Section 13
- Electronic Devices and Circuits - Section 24
- Electronic Devices and Circuits - Section 23
- Electronic Devices and Circuits - Section 22
- Electronic Devices and Circuits - Section 21
- Electronic Devices and Circuits - Section 20
- Electronic Devices and Circuits - Section 19
- Electronic Devices and Circuits - Section 18
- Electronic Devices and Circuits - Section 17
- Electronic Devices and Circuits - Section 16
- Electronic Devices and Circuits - Section 15
- Electronic Devices and Circuits - Section 14
- Electronic Devices and Circuits - Section 1
- Electronic Devices and Circuits - Section 12
- Electronic Devices and Circuits - Section 11
- Electronic Devices and Circuits - Section 10
- Electronic Devices and Circuits - Section 9
- Electronic Devices and Circuits - Section 8
- Electronic Devices and Circuits - Section 7
- Electronic Devices and Circuits - Section 6
- Electronic Devices and Circuits - Section 5
- Electronic Devices and Circuits - Section 4
- Electronic Devices and Circuits - Section 3
- Electronic Devices and Circuits - Section 2
41.
In a 4 bit counter the output of 3 JK FFs from MSB downward are connected to the NAND gate whose O/P is connected to CLR
42.
For checking the parity of a digital word, it is preferable to use
43.
Among the digital IC families - ECL, TTL, and CMOS
44.
In ASCII, letter B is coded as
45.
The power dissipated per gate
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