Electronics and Communication Engineering - Digital Electronics - Discussion
Discussion Forum : Digital Electronics - Section 2 (Q.No. 9)
9.
For a MOD-12 counter, the FF has a tpd = 60 ns The NAND gate has a tpd of 25 n sec. The clock frequency is
Answer: Option
Explanation:
For a proper working, the clock period should be equal to or greater than
tpd = Mod 12 - 4FFs = 4 x 60 = 240 nsec.
Total tpd = 240 + 25 = 265 nsec.
= fc
and fc = 3.774 MHz.
Discussion:
7 comments Page 1 of 1.
Om prakash said:
9 years ago
For a proper working, the clock period should be equal to or greater than 265 ns. Hence frequency < = 3.774 MHz.
Akash said:
9 years ago
4 flip flops how?
Tushar Yadav said:
9 years ago
@Akash
4 flipflops because MOD-12 counter = MOD-N where N=12,
and by rule, N <= 2^n,
12 <= 2^4.
Hence, n = 4 & thus 4 FFs.
4 flipflops because MOD-12 counter = MOD-N where N=12,
and by rule, N <= 2^n,
12 <= 2^4.
Hence, n = 4 & thus 4 FFs.
G.Bhargavi said:
8 years ago
Please, give more explanation.
Manjusree said:
7 years ago
MOD-12 counts 0 to 11.11 in binary is 1011. Each bit needs one flip-flop. So, to count from 0 to 11 we need 4 flip-flops. Given that Tpd for FF is 60ns. Tpd of NAND is 25ns.
For 4 FF Tpd= 4*60= 240ns.
Total Tpd= 240+25=265ns.
The clock frequency = 1/Tpd = 1/265ns = 3.774 MHz.
For 4 FF Tpd= 4*60= 240ns.
Total Tpd= 240+25=265ns.
The clock frequency = 1/Tpd = 1/265ns = 3.774 MHz.
(1)
Saini said:
7 years ago
Nice explanation, Thanks @Manjusree.
Rgiri said:
7 years ago
According to me, it is < 3.773, if frequency due to delay itself causing that much freq means, normal working might have less than that freq. 3.773.
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