Electronic Devices - Field-Effect Transistors - Discussion
Discussion Forum : Field-Effect Transistors - General Questions (Q.No. 30)
30.
If VD is less than expected (normal) for a self-biased JFET circuit, then it could be caused by a(n)
Discussion:
2 comments Page 1 of 1.
Millize said:
4 years ago
In a self-bias circuit. Vgs=-IdRs, Vgs and Vs are numerically equal, but has different polarity.
VD can be obtained by using the formula VDS=VD-VS; VD = VDS+VS; If gate lead is open then Vgs would be 0 since it would be isolated from the Drain and Source.
Since Vgs is numerically equal to Vs, if Vgs is 0, Vs is also 0 which then leads to VD getting a value less than what is expected since VD =VDS+0.
VD can be obtained by using the formula VDS=VD-VS; VD = VDS+VS; If gate lead is open then Vgs would be 0 since it would be isolated from the Drain and Source.
Since Vgs is numerically equal to Vs, if Vgs is 0, Vs is also 0 which then leads to VD getting a value less than what is expected since VD =VDS+0.
Sreenivas said:
1 decade ago
Please provide explanation for this question with self biased jfet circuit.
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