Digital Electronics - Shift Registers - Discussion
Discussion Forum : Shift Registers - General Questions (Q.No. 2)
2.
The bit sequence 0010 is serially entered (right-most bit first) into a 4-bit parallel out shift register that is initially clear. What are the Q outputs after two clock pulses?
Discussion:
10 comments Page 1 of 1.
Gurumalar said:
7 years ago
In 4bit parallel shift registers the values are <9 we should add0110. So,
0010+0110 = 1000.
0010+0110 = 1000.
(1)
Narasimha said:
8 years ago
It's very simple.
Initially, assume 0000 in the register. The Question says that out of 0010, they first perform 0 bit followed by 1. Let's see, after 1st clock pulse, the output display as 0*000. Then after second clock pulse, the output display as 1*000.
So, our answer is 1000.
* means TRANSMITTED/Shifted BIT.
Initially, assume 0000 in the register. The Question says that out of 0010, they first perform 0 bit followed by 1. Let's see, after 1st clock pulse, the output display as 0*000. Then after second clock pulse, the output display as 1*000.
So, our answer is 1000.
* means TRANSMITTED/Shifted BIT.
(3)
Lekshmi said:
8 years ago
@Keerthi.
Please explain the third clock pulse o/p and fourth clock pulse o/p.
Please explain the third clock pulse o/p and fourth clock pulse o/p.
(2)
Arjun said:
9 years ago
@Megha.
I can't understand your solution. Please explain it clearly.
I can't understand your solution. Please explain it clearly.
Shubham said:
9 years ago
It's simple, assume initial outputs are 0000 (Q0, Q1, Q2, Q3) first of all it is serial in, so for the 1st clock rightmost bit of input i.e 0 is inserted.
SO OUTPUT BECOMES 0000 then in 2nd clock 1 is inserted and the output becomes 1000.
So answer is C in short initially -> 0 0 0 0 in 1 st clock ->0 0 0 0 in 2nd clock -> 1 0 0 0.
SO OUTPUT BECOMES 0000 then in 2nd clock 1 is inserted and the output becomes 1000.
So answer is C in short initially -> 0 0 0 0 in 1 st clock ->0 0 0 0 in 2nd clock -> 1 0 0 0.
(1)
Keerthi said:
1 decade ago
1st time all the FF clear i.e) 0 states and then we give the i/p 0010.
As 1st clk the o/p is 0000 and then the 2nd clk the o/p is 1000.
3rd clk the o/p is 0100...4th clk the o/p is 0010.
As 1st clk the o/p is 0000 and then the 2nd clk the o/p is 1000.
3rd clk the o/p is 0100...4th clk the o/p is 0010.
(1)
Venkatesh said:
1 decade ago
Question 1 : Answer since q3=1 its complement will be q3=0 it is fed to q0.after fifth clock pulse q0=0.and q0=0(previous) was pushed to q1 so q1=0 and q1=1 is pushed to q2 the q2=1 and q2=1 is pushed to q3=1.
q0=0 q1=0 q2=1 q3=1.
q0=0 q1=0 q2=1 q3=1.
Megha said:
1 decade ago
First of all right most bit of 0010 that is 0 is sent. Due to parallel data out after 1 clock pulse output will be 0000. Now for second clock pulse second bit from right '1' is sent so similarly parallel data output '1000' will be the Result.
Priya said:
1 decade ago
After reset what is the result. I don't understand it.
Mukesh said:
1 decade ago
Reason is most simple for this. Serially two bits are in that is 0 followed by 1. Dey will demain at leftmost two bits of parral outcome and rest two bits will b zero.
I. E 1000.
I. E 1000.
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