Digital Electronics - Shift Registers - Discussion
Discussion Forum : Shift Registers - General Questions (Q.No. 7)
7.
What is meant by parallel load of a shift register?
Discussion:
3 comments Page 1 of 1.
Vinod said:
10 years ago
The name itself suggests that data is parallely loaded which means that if one of the ff of a n- bit register with parallely load is loaded with a bit then simultaneously all the off as will be loaded with the same value at that particular clock pulse.
Ram said:
10 years ago
Any one clearly explain this answer?
Riya said:
1 decade ago
At Preset condition, o/ps of flip-flops will be 1.
Preset = 1 means Q = 1..thus i/p is definitely 1.
When clr = 1 then Qbar = 1.
Preset = 1 means Q = 1..thus i/p is definitely 1.
When clr = 1 then Qbar = 1.
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