Digital Electronics - Logic Gates - Discussion
Discussion Forum : Logic Gates - General Questions (Q.No. 34)
34.
A clock signal with a period of 1 
s is applied to the input of an enable gate. The output must contain six pulses. How long must the enable pulse be active?
s is applied to the input of an enable gate. The output must contain six pulses. How long must the enable pulse be active?Enable must be active for 0 s.
s.Enable must be active for 3 s.
s.Enable must be active for 6 s.
s.Enable must be active for 12 s.
s.Discussion:
10 comments Page 1 of 1.
Vinod said:
1 decade ago
To all,
1 pulse dosen't mean a positive half part.
It means a complete period of pulse. So if output needs 6 pulses the enable need to be active for 6 times i.e 6*1us.
1 pulse dosen't mean a positive half part.
It means a complete period of pulse. So if output needs 6 pulses the enable need to be active for 6 times i.e 6*1us.
Sathiyam said:
1 decade ago
Ya in that clock period = 1us i.e. 0.5us for ON time of clock and 0.5us for OFF time. So as per question 6 pulse they need enable so Enable must be active for 6 us.
Sindu said:
7 years ago
How it can be possible to have the answer as 6 μs if there are 3μs in the inactive state?
Can anybody explain how it can be possible?
Can anybody explain how it can be possible?
Prathyu said:
1 decade ago
Output must contain six pulses means it must be active for six pulses so that input must be active for 6 micro sec.
PRITHA said:
8 years ago
I think B is the correct answer. Because in that 6μs the pulse was in the inactive state for 3μs.
Bindu said:
1 decade ago
For one cycle the delay is one micro second.
M.a.jayakrishnan said:
8 years ago
Explain it please.
Syed Shakeeb said:
3 years ago
Thanks @Prathyu.
Jay said:
1 decade ago
Please explain.
Divyanshu said:
1 decade ago
Explain ??
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