Digital Electronics - Logic Gates - Discussion
Discussion Forum : Logic Gates - General Questions (Q.No. 15)
15.
The power dissipation, PD, of a logic gate is the product of the ________.
Discussion:
3 comments Page 1 of 1.
Syed Shakeeb said:
3 years ago
The Power equals voltage and current.
Kalwa vikas said:
1 decade ago
Power Dissipation is an important metric for two reasons. Amount of current and power available in a battery is nearly constant. Power dissipation of a circuit or system defines battery life, The greater the power dissipation, the shorter the battery life. Power dissipation is proportional to the heat generated by the chip or system, Excessive heat dissipation may increase operating temperature and cause gate circuitry to drift out of its normal operating range, will cause gates to generate improper output values. Thus power dissipation of any gate implementation must be kept as low as possible.
Other this, power dissipation can be classified into static power dissipation and Dynamic power dissipation.
Ps (Static Power Dissipation) : Power consumed when the output or input are not changing or rather when clock is turned off. Normally static power dissipation is caused by leakage current. (As we reduce the transistor size, i.e. below 90nm, leakage current could be as high as 40% of total power dissipation).
Pd (Dynamic Power Dissipation) : Power consumed during output and input transitions, So we can say Pd is actual power i.e. power consumed by transistors + leakage current.
Thus total power dissipation is
Total power dissipation = static power dissipation + dynamic power dissipation.
Other this, power dissipation can be classified into static power dissipation and Dynamic power dissipation.
Ps (Static Power Dissipation) : Power consumed when the output or input are not changing or rather when clock is turned off. Normally static power dissipation is caused by leakage current. (As we reduce the transistor size, i.e. below 90nm, leakage current could be as high as 40% of total power dissipation).
Pd (Dynamic Power Dissipation) : Power consumed during output and input transitions, So we can say Pd is actual power i.e. power consumed by transistors + leakage current.
Thus total power dissipation is
Total power dissipation = static power dissipation + dynamic power dissipation.
Kalwa vikas said:
1 decade ago
Each gate is connected to a power supply VCC (VDD in the case of CMOS). Draws a certain amount of current during its operation. Since each gate can be in a High state, Transition or Low state, There are three distinguish currents drawn from power supply.
ICCH : Current drawn during HIGH state.
ICCT: Current drawn during HIGH to LOW, LOW to HIGH Transition.
ICCL : Current drawn during LOW state.
For TTL, ICCT the transition current is negligible, in comparison to ICCH and ICCL. If we assume that ICCH and ICCL are equal then,
Average Power Dissipation = Vcc * (ICCH + ICCL)/2
For CMOS, ICCH and ICCL current is negligible, in comparison to ICCT. So the Average power dissipation is calculated as below.
Average Power Dissipation = Vcc * ICCT.
So for TTL like logics family, power dissipation does not depend on frequency of operation, and for CMOS the power dissipation depends on the operation frequency.
ICCH : Current drawn during HIGH state.
ICCT: Current drawn during HIGH to LOW, LOW to HIGH Transition.
ICCL : Current drawn during LOW state.
For TTL, ICCT the transition current is negligible, in comparison to ICCH and ICCL. If we assume that ICCH and ICCL are equal then,
Average Power Dissipation = Vcc * (ICCH + ICCL)/2
For CMOS, ICCH and ICCL current is negligible, in comparison to ICCT. So the Average power dissipation is calculated as below.
Average Power Dissipation = Vcc * ICCT.
So for TTL like logics family, power dissipation does not depend on frequency of operation, and for CMOS the power dissipation depends on the operation frequency.
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