Digital Electronics - Digital Concepts - Discussion
Discussion Forum : Digital Concepts - General Questions (Q.No. 38)
38.
What is the typical invalid voltage for a binary signal?
Discussion:
16 comments Page 1 of 2.
Fatema said:
5 years ago
The voltage range for the binary signal are:
0 to 0.8 >> Low >> Logic 0 An output voltage 0.8 volts or less is considered to be logic "0".
0.8 to 2 >> invalid Voltages between 0.8 volts and 2.0 volts are considered invalid (illegal).
2 to 3.5 >> High >> Logic 1 When digital logic has an output voltage of two volts or above its output is Considered to be logic "1'.
0 to 0.8 >> Low >> Logic 0 An output voltage 0.8 volts or less is considered to be logic "0".
0.8 to 2 >> invalid Voltages between 0.8 volts and 2.0 volts are considered invalid (illegal).
2 to 3.5 >> High >> Logic 1 When digital logic has an output voltage of two volts or above its output is Considered to be logic "1'.
(3)
Swapnil said:
1 decade ago
I think a thumb rule is that the difference between logic 0 & logic 1 voltages should be atleast <1.5-2 V. In any case, the logic 0 & logic 1 should have a non-ambiguous margin. For 0.8-2 V, the margin is 1.2 V, which may be considered invalid by this logic.
On other hand, every logic family has a specified minimum voltage specification. That determines the range for said family.
On other hand, every logic family has a specified minimum voltage specification. That determines the range for said family.
Aan said:
1 decade ago
In digital circuit there are almost three families cmos, TTL, ECL and the region occurs between low to high is invalid region.
In TTL low voltage is 0 to 0.8V for logic 0 and high voltage is 2 to Vcc for logic 1. so there is a transition region between .8v to 2v. hence it is invalid region.
In TTL low voltage is 0 to 0.8V for logic 0 and high voltage is 2 to Vcc for logic 1. so there is a transition region between .8v to 2v. hence it is invalid region.
Amit said:
1 decade ago
Examples of binary logic levels:
Technology | L voltage | H voltage | Notes.
CMOS | 0 V to VDD/2 | VDD/2 to VDD | VDD = supply voltage.
TTL | 0 V to 0.8 V | 2 V to VCC | VCC is 4.75 V to 5.25 V.
ECL | -1.175 V to VEE | 0.75 V to 0 V | VEE is about -5.2 V. VCC=Ground.
Technology | L voltage | H voltage | Notes.
CMOS | 0 V to VDD/2 | VDD/2 to VDD | VDD = supply voltage.
TTL | 0 V to 0.8 V | 2 V to VCC | VCC is 4.75 V to 5.25 V.
ECL | -1.175 V to VEE | 0.75 V to 0 V | VEE is about -5.2 V. VCC=Ground.
Nisha said:
1 decade ago
It is usual to allow some tolerance in the voltage levels used; for example, 0 to 2 volts might represent logic 0, and 3 to 5 volts logic 1. A voltage of 2 to 3 volts would be invalid, and occur only in a fault condition or during a logic level transition.
Amrinder singh said:
1 decade ago
I think sometime this difference which is given is 1. 2 can be overcome by noise signal. So there is a standard difference b/w high and low value which is to be more than 1.5 volts.
Sougata Roy said:
1 decade ago
Range is very less for on to off(if off state is 0.8 then on state should be greater than 1.5 volts for off range value, hence we cannot take a range from 0.8v - 2 v).
Electronics boy said:
1 decade ago
It depends on the ciruit and its spec. If the ASIC swings b/w this voltages and able to identify HIGH and LOW within Vih(min) and Vil(max)it is accepted.
Shivani said:
1 decade ago
Please give its explanation.
Mahi said:
7 years ago
Thanks @Nisha, @Amit.
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