IndiaBIX

Digital Electronics - Digital Arithmetic Operations and Circuits

Exercise : Digital Arithmetic Operations and Circuits - General Questions
61.
Convert each of the decimal numbers to two's-complement form and perform the addition in binary.
+13 –10
add –7 add +15
0001  0100    0000  0101
0000  0110    0001  1001
0000  0110    0000  0101
1111  0110    1111  0101
Answer: Option
Explanation:
No answer description is available. Let's discuss.
62.
Add the following binary numbers.
0010 0110   0011 1011   0011 1100
+0101 0101   +0001 1110   +0001 1111
0111 1011    0100  0001    0101  1011
0111 1011    0101  1001    0101  1011
0111 0111    0101  1001    0101  1011
0111 0111    0100  0001    0101  1011
Answer: Option
Explanation:
No answer description is available. Let's discuss.
63.
The carry propagation delay in full-adder circuits:
is normally not a consideration because the delays are usually in the nanosecond range.
decreases in a direct ratio to the total number of FA stages.
is cumulative for each stage and limits the speed at which arithmetic operations are performed.
increases in a direct ratio to the total number of FA stages but is not a factor in limiting the speed of arithmetic operations.
Answer: Option
Explanation:
No answer description is available. Let's discuss.
64.
What is the difference between a full-adder and a half-adder?
Half-adder has a carry-in.
Full-adder has a carry-in.
Half-adder does not have a carry-out.
Full-adder does not have a carry-out.
Answer: Option
Explanation:
No answer description is available. Let's discuss.
65.
The summing outputs of a half- or full-adder are designated by which Greek symbol?
omega
theta
lambda
sigma
Answer: Option
Explanation:
No answer description is available. Let's discuss.
Quick links
Quantitative Aptitude
Verbal (English)
Reasoning
Programming
Interview
Placement Papers