# Digital Electronics - Digital Arithmetic Operations and Circuits

### Exercise :: Digital Arithmetic Operations and Circuits - General Questions

61.

Convert each of the decimal numbers to two's-complement form and perform the addition in binary.

 A. 0001  0100    0000  0101 B. 0000  0110    0001  1001 C. 0000  0110    0000  0101 D. 1111  0110    1111  0101

Explanation:

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62.

 0010 0110 0011 1011 0011 1100 +0101 0101 +0001 1110 +0001 1111

 A. 0111 1011    0100  0001    0101  1011 B. 0111 1011    0101  1001    0101  1011 C. 0111 0111    0101  1001    0101  1011 D. 0111 0111    0100  0001    0101  1011

Explanation:

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63.

The carry propagation delay in full-adder circuits:

 A. is normally not a consideration because the delays are usually in the nanosecond range. B. decreases in a direct ratio to the total number of FA stages. C. is cumulative for each stage and limits the speed at which arithmetic operations are performed. D. increases in a direct ratio to the total number of FA stages but is not a factor in limiting the speed of arithmetic operations.

Explanation:

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64.

 A. Half-adder has a carry-in. B. Full-adder has a carry-in. C. Half-adder does not have a carry-out. D. Full-adder does not have a carry-out.

Explanation:

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65.

The summing outputs of a half- or full-adder are designated by which Greek symbol?

 A. omega B. theta C. lambda D. sigma