Digital Electronics - Describing Logic Circuits - Discussion
Discussion Forum : Describing Logic Circuits - General Questions (Q.No. 12)
12.
How are the statements between BEGIN and END not evaluated in VHDL?
Discussion:
5 comments Page 1 of 1.
Pri said:
1 decade ago
In VHDL statements appear outside process will be executed concurrently. But inside process sequential execution. In question no process statement is given between begin and end so it is not evaluated sequentially.
Kirti said:
1 decade ago
Process is a concurrent statement but in it it execute sequentially.
Priyanka rai said:
1 decade ago
In which topic of digital we have to particularly learn about vhdl? please help.
Muskaan said:
1 decade ago
Sequential evaluation would occur only inside PROCESS block otherwise they are all evaluated concurrently, simultaneously, constantly.
Prasad said:
1 decade ago
Can anyone please justify the answer ?
Because, in VHDL modeling styles Sequential Statements are also used.
Because, in VHDL modeling styles Sequential Statements are also used.
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