Digital Electronics - Describing Logic Circuits - Discussion
Discussion Forum : Describing Logic Circuits - General Questions (Q.No. 8)
8.
In VHDL, the mode of a port does not define:
Discussion:
3 comments Page 1 of 1.
Priya said:
7 years ago
Please explain the syntax for vhdl.
Muskaan said:
1 decade ago
In VHDL, the Port Mode gives the direction of the signal and also
specifies the direction of signal transfer. There are 4 modes :-
1) In
2) Out
3) InOut
4) Buffer
It is defined by :-
PORT(a,b,cin: IN BIT; sum: OUT BIT; cout: OUT BIT);
But for defining TYPE of bit (i.e. 1 or 0) we use :-
TYPE BIT is ('0','1')
specifies the direction of signal transfer. There are 4 modes :-
1) In
2) Out
3) InOut
4) Buffer
It is defined by :-
PORT(a,b,cin: IN BIT; sum: OUT BIT; cout: OUT BIT);
But for defining TYPE of bit (i.e. 1 or 0) we use :-
TYPE BIT is ('0','1')
Suriya said:
1 decade ago
Someone can please explain me syntax of hdl, vhdl and verilog.
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