Digital Electronics - Combinational Logic Circuits

Exercise : Combinational Logic Circuits - General Questions
46.

The device shown here is most likely a ________.

comparator
multiplexer
demultiplexer
parity generator
Answer: Option
Explanation:
No answer description is available. Let's discuss.

47.
The design concept of using building blocks of circuits in a PLD program is called a(n):
hierarchical design.
architectural design.
digital design.
verilog.
Answer: Option
Explanation:
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48.
When adding an even parity bit to the code 110010, the result is ________.
1110010
1111001
110010
001101
Answer: Option
Explanation:
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49.
Which of the following combinations of logic gates can decode binary 1101?
One 4-input AND gate
One 4-input AND gate, one OR gate
One 4-input NAND gate, one inverter
One 4-input AND gate, one inverter
Answer: Option
Explanation:
No answer description is available. Let's discuss.

50.
What is the indication of a short to ground in the output of a driving gate?
Only the output of the defective gate is affected.
There is a signal loss to all load gates.
The node may be stuck in either the HIGH or the LOW state.
The affected node will be stuck in the HIGH state.
Answer: Option
Explanation:
No answer description is available. Let's discuss.