Placement Papers - Wipro

WIPRO VLSI PATTERN & INTERVIEW - 24 JUL 2006 - BANGALORE
Posted by :
Ravi Deepika
(4)
THANKS TO Friends AND MADAM
WIPRO VLSI is one of best vlsi labs in Bangalore. RECENTLY OPENED WI-FI LAB ALSO. so they visit our college (rvce), pesit and few others. So if wanna be in hardware line be sure to grab it. pay is too less. don worry, work is awesome.
Test :
normal wipro tech -- paper itself.
Interview :
2 sets of panels - VLSI & IT
SO U HAVE TO CHOOSE PANEL BEFORE TEST .
I got into vlsi division ...... so here it is ----
he asked me 3q on gates (universal - why?)
FLIP FLOP, DIVIDE BY 3 COUNTER WITH 50% DUTY CYCLE
TRANSISTORS - SWITCHING RELATED
analog & digi communication
VLSI ( VERY IMPORTANT)
PROJECT( 20 MINUTES)
TOTAL -- 45 MIN INTERVIEW
HR IS JUST FORMAL -- 2 MINUTES FOR VLSI DIVISION
NO ONE GOT ELIMINATED IN HR OUT OF 14 (VLSI) IN RVCE.
if u have good project u can draw him into it and waste 30 min in interview. so do some project. Dont fake projects as 2 of my friends were fired in interview because of that.
IN PROJECTS HE WILL ASK U TO MODEL CIRCUIT MATHEMATICALLY, FIND PROB OF ERROR IN COMM PROJECTS. SO BE PREPARED.
WIPRO VLSI is one of best vlsi labs in Bangalore. RECENTLY OPENED WI-FI LAB ALSO. so they visit our college (rvce), pesit and few others. So if wanna be in hardware line be sure to grab it. pay is too less. don worry, work is awesome.
Test :
normal wipro tech -- paper itself.
Interview :
2 sets of panels - VLSI & IT
SO U HAVE TO CHOOSE PANEL BEFORE TEST .
I got into vlsi division ...... so here it is ----
he asked me 3q on gates (universal - why?)
FLIP FLOP, DIVIDE BY 3 COUNTER WITH 50% DUTY CYCLE
TRANSISTORS - SWITCHING RELATED
analog & digi communication
VLSI ( VERY IMPORTANT)
PROJECT( 20 MINUTES)
TOTAL -- 45 MIN INTERVIEW
HR IS JUST FORMAL -- 2 MINUTES FOR VLSI DIVISION
NO ONE GOT ELIMINATED IN HR OUT OF 14 (VLSI) IN RVCE.
if u have good project u can draw him into it and waste 30 min in interview. so do some project. Dont fake projects as 2 of my friends were fired in interview because of that.
IN PROJECTS HE WILL ASK U TO MODEL CIRCUIT MATHEMATICALLY, FIND PROB OF ERROR IN COMM PROJECTS. SO BE PREPARED.
Quick links
Quantitative Aptitude
Verbal (English)
Reasoning
Programming
Interview
Placement Papers