Electronics and Communication Engineering - Digital Electronics - Discussion

Discussion Forum : Digital Electronics - Section 22 (Q.No. 32)
32.
In level clocking the output can change
on rising edge of clock cycle
on falling edge of clock cycle
during entire half cycle of the clock
none of the above
Answer: Option
Explanation:
No answer description is available. Let's discuss.
Discussion:
Be the first person to comment on this question !

Post your comments here:

Your comments will be displayed after verification.