Digital Electronics - Programmable Logic Device

Exercise : Programmable Logic Device - Filling the Blanks
21.
Full custom ICs can operate at ________ and require the ________.
lowest speed, largest die area
lowest speed, smallest die area
highest speed, largest die area
highest speed, smallest die area
Answer: Option
Explanation:
No answer description is available. Let's discuss.

22.
Gated arrays are ________ circuits that offer hundreds of thousands of gates.
VLSI
full custom
LSI
ULSI
Answer: Option
Explanation:
No answer description is available. Let's discuss.

23.
The MAX+PLUS II compiler will automatically program a macrocell to borrow up to ________ product terms from each of the 3 adjacent macrocells in the same LAB.
4
5
6
7
Answer: Option
Explanation:
No answer description is available. Let's discuss.

24.
A complex programmable logic device that consists of multiple SPLD arrays with programmable interconnections is called a ________.
bed-of-nails
boundary scan
CLB
CPLD
Answer: Option
Explanation:
No answer description is available. Let's discuss.

25.
Design costs for standard cell ASICs are ________ those for MPGAs.
lower than
about the same as
higher than
none of the above
Answer: Option
Explanation:
No answer description is available. Let's discuss.