Digital Electronics - Programmable Logic Device

Exercise : Programmable Logic Device - Filling the Blanks
6.
A GAL22V10 ________.
has up to 32 inputs and 10 outputs
is a type of SPLD
has 10 inputs and 22 outputs
is downloadable from the manufacturer's Web site
Answer: Option
Explanation:
No answer description is available. Let's discuss.

7.
Most FPGA logic modules utilize a(n) ________ approach to create the desired logic functions.
AND array
Look-up table
OR array
AND and OR array
Answer: Option
Explanation:
No answer description is available. Let's discuss.

8.
An EPM 7128S in a ________ PQFP package has 12 I/O per LAB plus 4 additional input-only pins for a total of 100 pins.
100-pin
120-pin
140-pin
160-pin
Answer: Option
Explanation:
No answer description is available. Let's discuss.

9.
A macrocell is ________.
part of a PAL or GAL
a type of one-time programmable SPLD
an example of intellectual property
a logic array block
Answer: Option
Explanation:
No answer description is available. Let's discuss.

10.
The final step in a design flow in which the logic design is implemented in the target device is called ________.
design entry
simulation
downloading
compiling
Answer: Option
Explanation:
No answer description is available. Let's discuss.