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Digital Electronics - Programmable Logic Device

Exercise : Programmable Logic Device - General Questions
51.
Which of the following is true?
Altera uses PAL architecture and Xilinx uses PLA architecture.
Altera uses PLA architecture and Xilinx uses PAL architecture.
Altera and Xilinx both use PAL architecture.
Altera and Xilinx both use PLA architecture.
Answer: Option
Explanation:
No answer description is available. Let's discuss.
52.
What is the status of a tristate output buffer on a MAX7000S family device?
It is permanently enabled or disabled.
It is controlled by one of the two global output enable pins.
It is controlled by other inputs or functions generated by other macrocells.
All of the above
Answer: Option
Explanation:
No answer description is available. Let's discuss.
53.
GAL is an acronym for ________.
Generic Array Logic
General Array Logic
Giant Array Logic
Generic Analysis Logic
Answer: Option
Explanation:
No answer description is available. Let's discuss.
54.
What gives a GAL its flexibility?
Its speed
Its reprogrammable EPROM
Its large logic arrays
Its programmable OLMCs
Answer: Option
Explanation:
No answer description is available. Let's discuss.
55.
What programmable technology is used in FPGA devices?
SRAM
FLASH
Antifuse
All of the above
Answer: Option
Explanation:
No answer description is available. Let's discuss.
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