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FREESCALE PAPER - 28 FEB 2008

Posted By : Sonu Gupta Rating : +38, -5
Hi Friends

1. Y=A.C+B.C(bar) the gate implementation was given.
How can this circuit is implemented by latch?

Ans:- Simple, this is simple 2:1 MUX Where A,B are inputs
And C is select pin or clock.

In Latch if clock is low its maintain output as its previous stage means no change.
So if connect output Y to A. then this is implemented by latch.

2. Set up time, hold time related 1 question.

3. Set up time, hold time was given and some delay in b/w
Max freq.=1/(transition delay+setup time) No hold time.

4. NAND circuit was implemented by MOS....Response was asked?

5. Power dissipation=V^2*f*C(load cap)

6. Delay =(1/W by L ratio)*Vth*C(load)

7. Two buffer ckt were given what is the difference b/w them?

8. CMOS inverter main yadi PMOS and NMOS ko interchange ker de to bo buffer bun jata hai.

9. Three ckts of inverter was give in which they asked about power dissipation....with ON time was 40% while off time 60%.
A. Simple CMOS inverter. B. Res was connected to VDD and PMOS
C. NMOS Connected to VDD and res.
So less on ckt was PMOS BECOZ ON TIME WAS 40% SO less power diss compare to C. While in A no res so very less power dissipation.



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