Online Digital Electronics Test - Digital Electronics Test 4



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Instruction:

  • Total number of questions : 20.
  • Time alloted : 30 minutes.
  • Each question carry 1 mark, no negative marks.
  • DO NOT refresh the page.
  • All the best :-).

1.

Once a signal is digitized, the information it contains does not ________ as it is processed.

A.
complain
B.
stiffen
C.
compress
D.
deteriorate

Your Answer: Option (Not Answered)

Correct Answer: Option D

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2.

A computer will use ASCII code to store information internally.

A.
True
B.
False

Your Answer: Option (Not Answered)

Correct Answer: Option B

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3.

The logic expression for a NOR gate is ________.

A.
B.
C.
D.

Your Answer: Option (Not Answered)

Correct Answer: Option D

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4.

It is important to memorize logic symbols, Boolean equations, and truth tables for logic gates.

A.
True
B.
False

Your Answer: Option (Not Answered)

Correct Answer: Option A

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5.

The output of an AND gate is HIGH when any input is HIGH.

A.
True
B.
False

Your Answer: Option (Not Answered)

Correct Answer: Option B

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6.

For the device shown here, assume the D input is LOW, both S inputs are LOW, and the input is LOW. What is the status of the outputs?

A.
All are HIGH.
B.
All are LOW.
C.
All but are LOW.
D.
All but are HIGH.

Your Answer: Option (Not Answered)

Correct Answer: Option D

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7.

Looping on a K-map always results in the elimination of:

A.
variables within the loop that appear only in their complemented form.
B.
variables that remain unchanged within the loop.
C.
variables within the loop that appear in both complemented and uncomplemented form.
D.
variables within the loop that appear only in their uncomplemented form.

Your Answer: Option (Not Answered)

Correct Answer: Option C

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8.

VHDL was created as a very flexible language and it allows us to define the operation of clocked devices in the code without relying on logic primitives.

A.
True
B.
False

Your Answer: Option (Not Answered)

Correct Answer: Option A

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9.

A(n) ________ one-shot starts a pulse in response to a trigger and will restart the internal pulse timer every time a subsequent trigger edge occurs before the pulse is complete.

A.
non-retriggerable
B.
retriggerable
C.
high-level triggered
D.
edge-triggered

Your Answer: Option (Not Answered)

Correct Answer: Option B

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10.

The condition occurring when two or more devices try to write data to a bus simultaneously is called ________.

A.
address decoding
B.
bus contention
C.
bus collisions
D.
address multiplexing

Your Answer: Option (Not Answered)

Correct Answer: Option B

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11.

Select the statement that best describes Read-Only Memory (ROM).

A.
nonvolatile, used to store information that changes during system operation
B.
nonvolatile, used to store information that does not change during system operation
C.
volatile, used to store information that changes during system operation
D.
volatile, used to store information that does not change during system operation

Your Answer: Option (Not Answered)

Correct Answer: Option B

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12.

ROMs retain data when the ________.

A.
power is off
B.
power is on
C.
system is down
D.
all of the above

Your Answer: Option (Not Answered)

Correct Answer: Option D

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13.

Address decoding for dynamic memory chip control may also be used for:

A.
controlling refresh circuits
B.
read and write control
C.
chip selection and address location
D.
memory mapping

Your Answer: Option (Not Answered)

Correct Answer: Option C

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14.

ROM access time is defined as ________.

A.
how long it takes to program the ROM chip
B.
being the difference between the READ and WRITE times
C.
the time it takes to get valid output data after a valid address is applied
D.
the time required to activate the address lines after the ENABLE line is at a valid level

Your Answer: Option (Not Answered)

Correct Answer: Option C

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15.

The JTAG signals are named TDI, TDO, TMS, and TCK.

A.
True
B.
False

Your Answer: Option (Not Answered)

Correct Answer: Option A

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16.

Most PAL devices have a tristate buffer driving the input pins.

A.
True
B.
False

Your Answer: Option (Not Answered)

Correct Answer: Option B

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17.

An EPM 7128S in a ________ PQFP package has 12 I/O per LAB plus 4 additional input-only pins for a total of 100 pins.

A.
100-pin
B.
120-pin
C.
140-pin
D.
160-pin

Your Answer: Option (Not Answered)

Correct Answer: Option D

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18.

The SUBDESIGN section defines the input and output of the logic circuit block.

A.
True
B.
False

Your Answer: Option (Not Answered)

Correct Answer: Option A

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19.

One CASE construct inside another CASE construct is called a do-loop.

A.
True
B.
False

Your Answer: Option (Not Answered)

Correct Answer: Option B

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20.

A logic circuit that provides a HIGH output if one input or the other input, but not both, is HIGH, is a(n):

A.
Ex-NOR gate
B.
OR gate
C.
Ex-OR gate
D.
NAND gate

Your Answer: Option (Not Answered)

Correct Answer: Option C

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