# Electronics - Flip-Flops and Timers

## Why Electronics Flip-Flops and Timers?

In this section you can learn and practice Electronics Questions based on "Flip-Flops and Timers" and improve your skills in order to face the interview, competitive examination and various entrance test (CAT, GATE, GRE, MAT, Bank Exam, Railway Exam etc.) with full confidence.

## Where can I get Electronics Flip-Flops and Timers questions and answers with explanation?

IndiaBIX provides you lots of fully solved Electronics (Flip-Flops and Timers) questions and answers with Explanation. Solved examples with detailed answer description, explanation are given and it would be easy to understand. All students, freshers can download Electronics Flip-Flops and Timers quiz questions with answers as PDF files and eBooks.

## Where can I get Electronics Flip-Flops and Timers Interview Questions and Answers (objective type, multiple choice)?

Here you can find objective type Electronics Flip-Flops and Timers questions and answers for interview and entrance examination. Multiple choice and true or false type questions are also provided.

## How to solve Electronics Flip-Flops and Timers problems?

You can easily solve all kind of Electronics questions based on Flip-Flops and Timers by practicing the objective type exercises given below, also get shortcut methods to solve Electronics Flip-Flops and Timers problems.

### Exercise :: Flip-Flops and Timers - General Questions

1.

Which of the following is correct for a gated D-type flip-flop?

 A. The Q output is either SET or RESET as soon as the D input goes HIGH or LOW. B. The output complement follows the input when enabled. C. Only one of the inputs can be HIGH at a time. D. The output toggles if one of the inputs is held HIGH.

Explanation:

No answer description available for this question. Let us discuss.

2.

When both inputs of a J-K flip-flop cycle, the output will:

 A. be invalid B. not change C. change D. toggle

Explanation:

No answer description available for this question. Let us discuss.

3.

Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?

 A. asynchronous operation B. low input voltages C. gate impedance D. cross coupling

Explanation:

No answer description available for this question. Let us discuss.

4.

The 555 timer can be used in which of the following configurations?

 A. astable, monostable B. monostable, bistable C. astable, toggled D. bistable, tristable

Explanation:

No answer description available for this question. Let us discuss.

5.

A basic S-R flip-flop can be constructed by cross-coupling which basic logic gates?

 A. AND or OR gates B. XOR or XNOR gates C. NOR or NAND gates D. AND or NOR gates