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Electronics - Flip-Flops and Timers

@ : Home > Electronics > Flip-Flops and Timers > General Questions

Exercise

"I do not seek. I find."
- Pablo Picasso
1. 

Which of the following is correct for a gated D-type flip-flop?

A. The Q output is either SET or RESET as soon as the D input goes HIGH or LOW.
B. The output complement follows the input when enabled.
C. Only one of the inputs can be HIGH at a time.
D. The output toggles if one of the inputs is held HIGH.

2. 

When both inputs of a J-K flip-flop cycle, the output will:

A. be invalid
B. not change
C. change
D. toggle

3. 

Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?

A. asynchronous operation
B. low input voltages
C. gate impedance
D. cross coupling

4. 

The 555 timer can be used in which of the following configurations?

A. astable, monostable
B. monostable, bistable
C. astable, toggled
D. bistable, tristable

5. 

A basic S-R flip-flop can be constructed by cross-coupling which basic logic gates?

A. AND or OR gates
B. XOR or XNOR gates
C. NOR or NAND gates
D. AND or NOR gates




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