This circuit is a master-slave D flip-flop. A D flip flop takes only a single input, the D (data) input. The master-slave configuration has the advantage of being edge-triggered, making it easier to use in larger circuits, since the inputs to a flip-flop often depend on the state of its output.
The circuit consists of two D flip-flops connected together. When the clock is high, the D input is stored in the first latch, but the second latch cannot change state. When the clock is low, the first latch's output is stored in the second latch, but the first latch cannot change state.
The result is that output can only change state when the clock makes a transition from high to low. -- Credits: Mr. Paul Falstad.
|Kidscorfield said: (Dec 17, 2016)|
|Can you show me how to merging single bit flip flops into multi bit flip flops using VHDL language?|
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