This circuit is a JK flip-flop. It only changes when the clock transitions from high to low. The inputs (labelled J and K) are shown on the left. When J = K = 0, it holds its present state. When J = 1, K = 0, the output is set to high. When J = 0, K = 1, the output is set to low. When J = K = 1, the output is toggled from high to low (or low to high). -- Credits: Mr. Paul Falstad.
|Shivaraj said: (Feb 24, 2011)|
|The j k flip flop is a basic flip flop which has no forbidden condition|
|Margus said: (Mar 13, 2011)|
|@Shivaraj Try `reset` button for this simulation and you get both outputs on high or low :P|
|Amina said: (Nov 13, 2012)|
|Design mod-10 up counter using negative edge JK flip flops with active low clear.|
|Dinesh said: (Feb 13, 2014)|
|A jk flip flop can be considered to be a counter of asynchronous mode with proper cascading connections.|
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