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Digital Electronics - Flip-Flops

@ : Home > Digital Electronics > Flip-Flops > General Questions

Exercise

"Time and tide wait for none."
- Alexander Pope
37. 

In a 555 timer, three 5 k resistors provide a trigger level of ________.

A. 1/4 VCC and a threshold level 1/2 VCC
B. 1/3 VCC and a threshold level 3/4 VCC
C. 1/3 VCC and a threshold level 2/3 VCC
D. 1/4 VCC and a threshold level 2/3 VCC

38. 

Does the cross-coupled NOR flip-flop have active-HIGH or active-LOW set and reset inputs?

A. active-HIGHB. active-LOW

39. 

The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the:

A. edge-detection circuit.
B. NOR latch.
C. NAND latch.
D. pulse-steering circuit.

40. 

With four J-K flip-flops wired as an asynchronous counter, the first output change of divider #4 indicates a count of how many input clock pulses?

A. 16B. 8
C. 4D. 2

41. 

What is the significance of the J and K terminals on the J-K flip-flop?

A. There is no known significance in their designations.
B. The J represents "jump," which is how the Q output reacts whenever the clock goes high and the J input is also HIGH.
C. The letters were chosen in honor of Jack Kilby, the inventory of the integrated circuit.
D. All of the other letters of the alphabet are already in use.

42. 

Why are the S and R inputs of a gated flip-flop said to be synchronous?

A. They must occur with the gate.
B. They occur independent of the gate.




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