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# Digital Electronics - Flip-Flops

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### Exercise

"Loneliness is the most terrible poverty."
- Mother Teresa
25.

Which of the following describes the operation of a positive edge-triggered D flip-flop?

 A. If both inputs are HIGH, the output will toggle. B. The output will follow the input on the leading edge of the clock. C. When both inputs are LOW, an invalid state exists. D. The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.

26.

What does the triangle on the clock input of a J-K flip-flop mean?

 A. level enabled B. edge-triggered

27.

A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________.

 A. constantly LOW B. constantly HIGH C. a 20 kHz square wave D. a 10 kHz square wave

28.

The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their ________ state(s) at the ________.

 A. opposite, active clock edge B. inverted, positive clock edge C. quiescent, negative clock edge D. reset, synchronous clock edge

29.

An RC circuit used in a nonretriggerable 74121 one-shot has an REXT of 49 k and a CEXT of 0.2 F. The pulse width (tW) is approximately ________.

 A. 6.9 s B. 6.9 ms C. 69 ms D. 690 ms

30.

On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________.

 A. the clock pulse is LOW B. the clock pulse is HIGH C. the clock pulse transitions from LOW to HIGH D. the clock pulse transitions from HIGH to LOW